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 STA1102R
3 Gbps, 2 differential-pair channel eSATA signal re-driver
Preliminary data
Features

Supports eSATA data rate of 1.5 Gbps and 3 Gbps Supports complete eSATA bus of two 2-wire differential-pair channels Squelch detector for validity of input differential signal Single operating supply (VCC) range of 3.3 V 10% Low power mode 100 CML I/Os eSATA hot-plug capable Low capacitance on all channels 1-bit input equalizer regenerates the receiver attenuated signal 1-bit adjustable pre-emphasis and driver to drive the transmitter outputs over long PCB track lengths Low output skew and jitter Low ground bounce QFN20 (4 x 4 mm)
Description
The STA1102R is a serial data signal re-driver. It integrates two differential-pair channels suitable for eSATA signals up to a 3 Gbps data rate, in compliance with the SATA rev 2.6 specification. An input detector is available at each channel, which constantly monitors the input signal level for output squelch functionality. If the detected differential input is below a defined threshold, the output is biased to the common mode voltage. High-speed data paths and the flow-through pinout minimize internal device jitter and simplify board layout. The integrated input equalizer improves signal integrity at the receiver due to effects from lossy cables. A 1-bit adjustable preemphasis is also integrated to drive the transmitter outputs over long PCB track lengths. The device can be set to a low-power mode by disabling the output current drivers through the EN pin.

Available in QFN20 (4 x 4 mm) package www..com with flow-through pinout footprint
-40 C to 85 C operating temperature range
Table 1.
Device summary
Order code Package QFN20 (4 x 4 mm) Packing Tape and reel
STA1102RQTR
October 2009
Doc ID 16470 Rev 1
1/17
www.st.com 17
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Block diagram
STA1102R
1
Block diagram
Figure 1. STA1102R block diagram
Squelch Detector
In_D1+ Equalizer In_D1Output Driver
Out_D1+ Out_D1-
D1 EN Low Power Mode Control
D2
Out_D2+ Out_D2-
In_D2+ Output Driver Equalizer In_D2-
Squelch Detector
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STA1102R Figure 2. Pin configuration - top view
Block diagram
VCC
GND
GND
GND
20
19
18
17
16
IN_D1+
1
VCC
15
OUT_D1+
IN_D1-
2
14
OUT_D1-
GND
3
13
GND
OUT_D2-
4
12
IN_D2-
OUT_D2+
5
11
IN_D2+
6
7
8
9
10
VCC
Table 2.
Pin description
Pin name IN_D1+ IN_D1GND OUT_D2OUT_D2+ VCC EN Type Input Input Power Output Output Power Input Function IN_D1+ makes a differential pair with IN_D1IN_D1- makes a differential pair with IN_D1+ Ground OUT_D2- makes a differential pair with OUT_D2+ OUT_D2+ makes a differential pair with OUT_D23.3 V DC supply Output driver enable pin; When low, device enters low power mode (internal 360 k pull-up resistor to VCC) Channel 2 pre-emphasis selection (internal 360 k pull-down resistor to GND) Channel 1 pre-emphasis selection (internal 360 k pull-down resistor to GND)
Pin number 1
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2 3 4 5 6 7
8 9
D2 D1
Input Input
Doc ID 16470 Rev 1
VCC
D1
D0
EN
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Block diagram Table 2. Pin description (continued)
Pin name VCC IN_D2+ IN_D2GND OUT_D1OUT_D1+ VCC GND GND GND VCC Type Power Input Input Power Output Output Power Power Power Power Power 3.3 V DC supply Function
STA1102R
Pin number 10 11 12 13 14 15 16 17 18 19 20
IN_D2+ makes a differential pair with IN_D2IN_D2- makes a differential pair with IN_D2+ Ground OUT_D1- makes a differential pair with OUT_D1+ OUT_D1+ makes a differential pair with OUT_D13.3 V DC supply Ground Ground Ground 3.3 V DC supply
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Doc ID 16470 Rev 1
STA1102R
Functional description
2
2.1
Functional description
Equalizer
The integrated input equalizer reduces system jitter and attenuation from long or lossy cables. Shaping is performed by the gain stage of the equalizer to compensate the signal.
2.2
Pre-emphasis
The STA1102R provides at each output a differential pair of 1-bit programmable preemphasis to compensate for losses across long PCB tracks and interconnects after the re-driver output. Below, the truth table of the pre-emphasis control is shown: Table 3.
EN 0 1 1 1 1
Pre-emphasis truth table
D0 x 0 0 1 1 D1 x 0 1 0 1 Functions Low power mode: Output driver disabled; output driven to HiZ Normal operation mode: both CH1 and CH2 0 dB pre-emphasis Normal operation mode: CH1 0 dB pre-emphasis; CH2 2.5 dB pre-emphasis Normal operation mode: CH1 2.5 dB pre-emphasis; CH2 0 dB pre-emphasis Normal operation mode: Both CH1 and CH2 2.5 dB pre-emphasis
2.3
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Input termination
The STA1102R integrates precise 50 10% termination resistors, pulled up to VCm, on all its differential input channels. External terminations are not required. This gives improved performance and also minimizes the PCB board space. These on-chip termination resistors should match the differential characteristic impedance of the transmission line.
Doc ID 16470 Rev 1
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Functional description
STA1102R
2.4
Low power modes
There are 2 types of low power modes in the STA1102R: hardware low and auto low power modes.
2.4.1
Hardware low power mode
The EN input activates a hardware low power mode. There is an internal pull-up resistor to maintain the EN in the default (HIGH) state. When this low power mode is activated (EN=L), all input and output buffers and internal bias circuitry are powered off and disabled. Outputs are driven to HiZ in low power mode. There is a delay associated with entering (max 2 s) and exiting (max 20 s) this hardware low power mode.
2.4.2
Auto low power mode
The auto low power mode is activated when differential voltage at either or both of the channels is < 50 mV for more than 3 s. During this low power mode, output of the associated channel is driven to Vcm and the selective circuit block is disabled to lower power consumption. The delay associated with exiting the auto low power mode is 50 ns max.
2.5
Squelch detector
A squelch detector is integrated on the input of each of the 2 data paths. The squelch detector is a high-speed amplitude comparator that is turned on when EN=H. The differential input signal is monitored by the detector. When the differential input is detected to be less than or equal to 50 mV, the input signal is considered an invalid signal and is not passed to the output. When this happens, the corresponding output is biased to VCM. When the differential input is greater than or equal to 150 mV, the input signal is considered valid signal and is passed to the output. The integration of the squelch detector helps the system to prevent responding to noises. As such, it enables the device to fully support OOB signaling.
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STA1102R
Application diagram
3
Application diagram
Figure 3. Typical application diagram
20
19
18
17
16
SATA HOST CONTROLLER
10nF
10nF
2
IN_D1-
OUT_D1- 14
10nF
3
13
10nF
4
OUT_D2-
IN_D2-
12
10nF
10nF
5
OUT_D2+ EN
6 7
IN_D2+ 11 D1
8
10nF
D0
9 10
3.3V
1uF
100nF
1nF
Typical circuit above is shown with CH1 pre-emphasis of 0 dB and CH2 pre-emphasis of 2.5 dB.
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Doc ID 16470 Rev 1
eSATA CONNECTOR
1
IN_D1+
OUT_D1+ 15
10nF
To GPIO
7/17
Absolute maximum ratings
STA1102R
4
Absolute maximum ratings
Absolute maximum ratings are those values above which damage to the device may occur. Functional operation under these conditions is not implied. All voltages are referenced to GND. Table 4.
Symbol VCC VI TSTG VESD Supply voltage to ground Differential pair IOs voltage range Control IOs voltage range Storage temperature Electrostatic discharge voltage (human body model)
Absolute maximum ratings
Parameter Value -0.5 to + 4.0 -0.5 to + 4.0 -0.5 to + 4.0 -65 to + 150 12 Unit V V V C kV
5
Thermal data
Table 5.
Symbol JA
QFN20 package thermal data
Parameter Thermal coefficient (junction-ambient) QFN20 60 Unit C/
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STA1102R
Recommended operating conditions
6
Recommended operating conditions
Table 6.
Symbol VCC TA CC DR
Recommended operating conditions
Parameter Supply voltage Operating ambient temperature Coupling capacitor Data rate Test conditions Min 3.0 0 Typ 3.3 12 Max 3.6 85 3.0 Unit V C nF Gbps
6.1
Electrical characteristics
(TA = 0 to 85 C, VCC = 3.0 V to 3.6 V unless otherwise specified). Table 7.
Symbol
DC electrical characteristic
Parameter Test conditions Min Typ Max Unit
General parameter characteristics ICC_standby Standby mode supply current EN = L VDIFF_RX=700 mV, K28.5 pattern running at 3 Gbps EN=H, D1=D0=H VDIFF_RX VTH, EN=H D1=D0=H Data propagation delay Device disable time Device enable time EN = H to L EN = L to H 300 A
ICC_active
Active mode supply current
-
-
80
mA
ICC_squelch TPD
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-
-
45 400 2 20
mA ps s s
TDIS TEN
Control logic characteristics VIH VIL IIH IIL Input logic high voltage Input logic low voltage Input logic high current Input logic low current 1.4 -15 -15 0.5 15 15 V V A A
Squelch detector characteristics VTH TENTER TEXIT Squelch threshold voltage Squelch mode enter Squelch mode exit 50 150 5 5 mVpp ns ns
Doc ID 16470 Rev 1
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Recommended operating conditions Table 7.
Symbol
STA1102R
DC electrical characteristic (continued)
Parameter Test conditions Min Typ Max Unit
AC/DC specifications for receiver VDIFF_RX VCM_RX ZDIFF_RX ZSE_RX Differential input peak-to-peak voltage Common mode voltage Differential input impedance Single-ended input impedance DR = 3.0 Gbps f = 100 MHz to 300 MHz f = 300 MHz to 600 MHz RLDIFF_RX Differential input return loss f = 600 MHz to 1200 MHz f = 1.2 GHz to 2.4 GHz f = 2.4 GHz to 3.0 GHz 200 85 40 18 14 10 8 3 0 100 1600 mVpp 115 V

dB dB dB dB dB
Table 8.
Symbol
AC electrical characteristic
Parameter Test conditions f = 100 MHz to 300 MHz f = 300 MHz to 600 MHz Min 5 5 2 1 1 67 Typ Max 136 50 Unit dB dB dB dB dB ps ps
RLCM_RX Common mode input return loss
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f = 600 MHz to 1200 MHz f = 1.2 GHz to 2.4 GHz f = 2.4 GHz to 3.0 GHz
TR/F_RX
Input rise/fall time
20% to 80% Mid-point of RX+ to mid-point of RX-
TSkew_RX Input differential skew AC/DC specifications for transmitter
Differential output peak-to-peak VDIFF_TX voltage
f = 1.5 GHz; D0/D1 = L f = 1.5 GHz; D0/D1 = H -
400 600 85
2.1 100
600 800 115
mVpp mVpp V
VCM_TX ZDIFF_TX
Common mode voltage Differential output impedance
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Doc ID 16470 Rev 1
STA1102R Table 8.
Symbol ZSE_TX
Recommended operating conditions AC electrical characteristic (continued)
Parameter Single-ended output impedance Test conditions f = 100 MHz to 300 MHz f = 300 MHz to 600 MHz RLDIFF_TX Differential output return loss f = 600 MHz to 1200 MHz f = 1.2 GHz to 2.4 GHz f = 2.4 GHz to 3.0 GHz f = 100 MHz to 300 MHz f = 300 MHz to 600 MHz RLCM_TX Common mode output return loss f = 600 MHz to 1200 MHz f = 1.2 GHz to 2.4 GHz f = 2.4 GHz to 3.0 GHz TR/F_TX Output rise/fall time 20% to 80% Mid-point of RX+ to mid-point of RXDR = 3 Gbps; K28.5 pattern DR = 3 Gbps; K28.5 pattern DR = 3 Gbps; K28.7 pattern Min 40 14 8 6 6 3 5 5 2 1 1 67 Typ 0.2 0.13 2.0 Max 136 20 0.3 0.2 2.15 Unit
dB dB dB dB dB dB dB dB dB dB ps ps UIpp UIpp psrms
TSkew_TX Output differential skew TJTX
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Total jitter Deterministic jitter Random jitter
DJTX RJTX
Doc ID 16470 Rev 1
11/17
Recommended operating conditions Figure 4. Jitter measurement setup
STA1102R
HOST
STA1102R
10" FR4 IN_D1 OUT_D2 OUT_D1 IN_D2 10" FR4
eSATA compliance measurement point
eSATA compliance measurement point
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12/17
Doc ID 16470 Rev 1
DEVICE
STA1102R
Package mechanical data
7
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Figure 5. Package outline for QFN20 (4 x 4 x 0.8 mm) - pitch 0.5 mm
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Package mechanical data Table 9. Mechanical data for QFN20 (4 x 4 x 0.8 mm) - pitch 0.5 mm
Millimeters Symbol Min A A1 A2 A3 b D D2 E E2 e L 0.45 0.30 Exposed pad variations D2 Variation Min A 2.70 Typ 2.80 Max 2.90 Min 2.70 Typ 2.80 E2 3.85 0.70 0.18 3.85 Typ 0.75 0.02 0.65 0.25 0.23 4.00 See exposed pad variations 4.00 See exposed pad variations 0.50 0.40
STA1102R
Max 0.80 0.30 4.15
4.15
0.55 0.50
Table 10.
Max 2.90
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Doc ID 16470 Rev 1
STA1102R Figure 6.
Package mechanical data Footprint recommendation for QFN20 (4 x 4 x 0.8 mm) - pitch 0.5 mm
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Doc ID 16470 Rev 1
15/17
Revision history
STA1102R
8
Revision history
Table 11.
Date 19-Oct-2009
Document revision history
Revision 1 Initial release. Changes
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16/17
Doc ID 16470 Rev 1
STA1102R
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
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Doc ID 16470 Rev 1
17/17


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